1. Field of the Invention
The embodiments of the present invention relate to a built-in self test (BIST) architecture, and particularly to compressing and applying deterministic automatic test pattern generation (ATPG) patterns in a logic BIST architecture.
2. Description of the Related Art
Larger and more complex logic designs in integrated circuits (ICs) lead to demands for more sophisticated testing to ensure fault-free performance of those ICs. This testing can represent a significant portion of the design, manufacture, and service cost of integrated circuits (ICs). In a simple model, testing of an IC can include applying multiple test patterns to the inputs of a circuit and monitoring its outputs to detect the occurrence of faults. Fault coverage indicates the efficacy of the test patterns in detecting each fault in a universe of potential faults. Thus, if a set of test patterns is able to detect substantially every potential fault, then fault coverage approaching 100% has been achieved.
To facilitate better fault coverage and minimize test cost, DFT (design-for-test) can be used. In one DFT technique, structures in the logic design can be used. Specifically, a logic design implemented in the IC generally includes a plurality of state elements, e.g. sequential storage elements like flip-flops. These state elements can be connected into scan chains of computed lengths, which vary based on the design. In one embodiment, all state elements in a design are scannable, i.e. each state element is in a scan chain. The state elements in the scan chains are typically called scan cells. In DFT, each scan chain includes a scan-input pin and a scan-output pin, which serve as control and observation nodes during the test mode.
The scan chains are loaded by clocking in predetermined logic signals through the scan cells. Thus, if each scan chain includes 500 scan cells, then 500 clock cycles are used to complete the loading process. Note that, for simplicity, the embodiments provided herein describe scan chains of equal length. In actual embodiments, DFT attempts to create, but infrequently achieves, this goal. Thus, in actual embodiments, software can compensate for the different scan chain lengths, thereby ensuring that outputs from each test pattern are recognized and analyzed accordingly. This methodology is known by those skilled in the art and therefore is not explained in detail herein.
The test patterns for the scan chains can be generated using an external testing device. Using such a device, an exhaustive test can be done by applying 2N input patterns to a design with N inputs and scan cells. However, this test approach rapidly becomes commercially impractical as the number of inputs increases.
To solve this problem, deterministic automatic test pattern generation (ATPG) can be used to generate the minimum set of patterns while providing fault coverage close to 100%. Specifically, in deterministic ATPG, each test pattern is designed to test for the maximum number of faults. However, even with the reduction in test patterns, deterministic ATPG patterns still require significant storage area in the test-application equipment (tester) for the large number of patterns that are input directly to the scan chains, and for the expected output values from the scan chains. Moreover, this test method has associated inefficiencies because of its off-chip access time.
Alternatively, and more frequently in current, complex ICs, structures can be added to the design that allow the IC to quickly test itself. These built-in self-test (BIST) structures can include various pattern generators, the most typical being a pseudorandom pattern generator (PRPG). After the patterns generated by the PRPG are propagated through the scan chains in the tested design, the outputs are analyzed to determine if a fault is detected.
FIG. 1A illustrates a logic BIST architecture 100 for testing a design 130 having six scan chains 131–136. In this embodiment, architecture 100 includes a linear feedback shift register (LFSR) 110 to implement the PRPG. PRPG-LFSR 110 includes a plurality of sequential storage elements (in a typical embodiment, flip-flops) 111–114 that are connected in series with a feedback loop and one XOR operation (indicated by the circled plus sign). As shown in FIG. 1A, the flow of signals in these interconnected flip-flops is from left to right. Note that a linear feedback shift register has a characteristic polynomial that is expressed in terms of its feedback connections. In this embodiment, PRPG-LFSR 110 implements the polynomial f(x)=x4+x3+1. Other embodiments can implement other polynomials, preferably primitive polynomials.
As shown in FIG. 1B, if an LFSR 180 generates bit sequences, i.e. the test patterns, directly for scan chains 181–184, then those bit sequences differ by only a few bits, i.e. phase shifts. These small phase shifts can undesirably reduce the fault coverage. As a result, in architecture 100, a phase shifter 120 is provided to transform the outputs of PRPG-LFSR 110 into uncorrelated signals. Phase shifter 120 is described in further detail in “Built-In Test for VLSI: Pseudorandom Techniques”, by P. H. Bardell et al., page 176, John Wiley & Sons, 1987. Thus, the values from PRPG-LFSR 110 are loaded into scan chains 131–136 in a manner controlled by the various XOR operations in phase shifter 120. In this embodiment, scan chain 131 includes an input scan pin si1 and an output scan pin so1. Scan chains 132–136 include corresponding scan pins si2/so2, si3/so3, si4/so4, si5/so5, and si6/so6, respectively.
Compactor 140 compacts the outputs from tested design 130 and provides inputs to a multiple input signature register (MISR) LFSR 150, which includes a plurality of storage elements 151–154 coupled in series with various XOR operations and feedback loops. In this embodiment, MISR-LFSR 150 implements the polynomial f(x)=x4+x+1. After several cycles, MISR-LFSR 150, described in further detail in “Built-In Test for VLSI: Pseudorandom Techniques”, by P. H. Bardell et al., page 119, John Wiley & Sons, 1987, provides a “signature” that is a near-unique checksum for a given sequence of its input values. At this point, the state of MISR-LFSR 150 can be compared to the known “signature” of the fault-free design, wherein a mismatch indicates that at least one erroneous value was unloaded from scan chains 131–136. This erroneous value can be used to determine that a fault exists in tested design 130.
FIG. 1C illustrates a graph plotting fault coverage versus number of pseudorandom test patterns. As seen in FIG. 1C, pseudorandom pattern generation has two disadvantages. First, the final fault coverage is signficantly less than 100%. Generally, a PRPG provides fault coverage in the range of 70–80%, which is unacceptable for many IC applications. Moreover, as the number of test patterns increases, the detection of faults becomes significantly less efficient. Specifically, pseudorandom pattern generation is very efficient in removing easy-to-detect faults from a fault list in the beginning of the test process, but is less efficient in removing hard-to-detect (i.e. circuit dependent) faults near the end of the test process. In fact, to achieve acceptable test coverage, the number of PRPG patterns must be significantly larger than the number of deterministic ATPG patterns to provide the same fault coverage. Therefore, using PRPG forces a trade-off between reduced test coverage and reduced tester storage data.
Several solutions have been proposed to address this problem, each having associated disadvantages. In one solution, the number of scan chains can be increased, thereby reducing the number of pattern load/unload clock cycles. However, the tester storage volume is still unreasonably large for typical industry applications. In a second solution, test points can be added to the design, thereby increasing the probability of fault detection by pseudorandom patterns. This solution is undesirable because it increases silicon area and the propagation delay of critical timing paths. In a third solution, the pseudorandom patterns can be biased or modified to test for random-resistant faults. However, this solution adds significant silicon area to the design and/or increases data volume stored in the tester. In a fourth solution, deterministic ATPG patterns can be added to BIST patterns for a more complete test coverage. However, this solution significantly increases the data volume stored in the tester.
Finally, in a fifth solution, the PRPG is initialized, i.e. seeded, such that predetermined scan cells are set to values, after a suitable number of cycles of the PRPG, that achieve detection of targeted faults. The values stored in these predetermined scan cells, called “care bits”, are typically much fewer (i.e. on the order of hundreds) than the “don't care bits” (i.e. on the order of hundreds of thousands) stored in the other scan cells. This solution is described in further detail in “LFSR-Coded Test Patterns for Scan Designs”, by B. Könemann, Munich 1991. Although improving test coverage, this solution requires storing a significant number of seeds for the PRPG to detect the care bits, thereby undesirably increasing the amount of stored data. Additionally, this solution requires serially loading the seeds into the PRPG. In FIG. 1A, four clock cycles are needed to load PRPG-LFSR 110. However, an actual implementation of PRPG-LFSR 110 could include hundreds of storage elements, thereby requiring a corresponding number of cycles to load. Thus, this solution can also significantly increase the test application time. Therefore, a need arises for a pseudorandom pattern generation system and method that minimizes test application time while achieving fault coverage comparable to deterministic ATPG.